CMOS (Complementary Metal-Oxide Semiconductor) circuits usually include PFETs (P-type Field-Effect Transistor) and NFETs (N-type Field-Effect Transistor). Usually, a PFET is formed in an Nwell (n-type region). The source of the PFET is usually connected to a power supply with a voltage VDD. The source of the PFET is usually p-type material. The Nwell where the PFET is formed is usually connected to the power supply VDD as well. Because the source of the PFET and the Nwell are both connected to VDD, the P/N junction (i.e. a diode) formed at the interface of the source of the PFET and the Nwell is not forwarded biased. Since the P/N junction is not forward biased, latch-up should not occur in this area.
As stated previously, the source of a PFET and the Nwell where the PFET is formed are usually connected to VDD. However, in some cases (e.g. testing of SRAM cells), the voltage applied at the Nwell of a PFET is different from the voltage VDD. In order to prevent latch-up in these cases, it is important that the P/N junction formed by the source of a PFET and the Nwell not be forward-biased during this testing or when powering up a circuit to operate at normal operating voltages.